SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
Each I2C module is comprised of both master and slave functions and is identified by a unique address. A master-initiated communication generates the clock signal, SCL. For proper operation, the SDA pin must be configured as an open-drain signal. Due to the internal circuitry that supports high-speed operation, the SCL pin must not be configured as an open-drain signal, although the internal circuitry causes it to act as if it were an open-drain signal. Both SDA and SCL signals must be connected to a positive supply voltage using a pullup resistor. Figure 19-2 shows a typical I2C bus configuration. See the I2C bus specification and user manual to determine the size of the pullups required for proper operation.