| 31-16 |
RESERVED |
R |
0x0 |
|
| 15-13 |
TCACT |
R/W |
0x0 |
Timer Compare Action Select.
0x0 = Disable compare operations.
0x1 = Toggle State on Time-Out
0x2 = Clear CCP on Time-Out
0x3 = Set CCP on Time-Out
0x4 = Set CCP immediately and toggle on Time-Out
0x5 = Clear CCP immediately and toggle on Time-Out
0x6 = Set CCP immediately and clear on Time-Out
0x7 = Clear CCP immediately and set on Time-Out
|
| 12 |
TACINTD |
R/W |
0x0 |
One-shot/Periodic Interrupt Disable.
0x0 = Time-out interrupt functions as normal.
0x1 = Time-out interrupt are disabled. Setting the TACINTD bit in the GPTMTAMR register does not have an effect on the µDMA or ADC interrupt time-out event trigger assertions. If the TATODMAEN bit is set in the GPTMDMAEV register or the TATOADCEN bit is set in the GPTMADCEV register, a µDMA or ADC time-out trigger is sent to the µDMA or ADC, respectively, even if the TACINTD bit is set.
|
| 11 |
TAPLO |
R/W |
0x0 |
GPTM Timer A PWM Legacy Operation.
This bit is only valid in PWM mode.
0x0 = Legacy operation with CCP pin driven Low when the GPTMTAILR is reloaded after the timer reaches 0.
0x1 = CCP is driven High when the GPTMTAILR is reloaded after the timer reaches 0.
|
| 10 |
TAMRSU |
R/W |
0x0 |
GPTM Timer A Match Register Update.
If the timer is disabled (TAEN is clear) when this bit is set, GPTMTAMATCHR and GPTMTAPR are updated when the timer is enabled.
If the timer is stalled (TASTALL is set), GPTMTAMATCHR and GPTMTAPR are updated according to the configuration of this bit.
0x0 = Update the GPTMTAMATCHR register and the GPTMTAPR register, if used, on the next cycle.
0x1 = Update the GPTMTAMATCHR register and the GPTMTAPR register, if used, on the next timeout.
|
| 9 |
TAPWMIE |
R/W |
0x0 |
GPTM Timer A PWM Interrupt Enable.
This bit enables interrupts in PWM mode on rising, falling, or both edges of the CCP output, as defined by the TAEVENT field in the GPTMCTL register.
In addition, when this bit is set and a capture event occurs, Timer A automatically generates triggers to the ADC and DMA if the trigger capability is enabled by setting the TAOTE bit in the GPTMCTL register and the CAEDMAEN bit in the GPTMDMAEV register, respectively.
This bit is only valid in PWM mode.
0x0 = Capture event interrupt is disabled.
0x1 = Capture event interrupt is enabled.
|
| 8 |
TAILD |
R/W |
0x0 |
GPTM Timer A Interval Load Write.
Note the state of this bit has no effect when counting up.
The bit descriptions above apply if the timer is enabled and running.
If the timer is disabled (TAEN is clear) when this bit is set, GPTMTAR GPTMTAV and GPTMTAPs, are updated when the timer is enabled.
If the timer is stalled (TASTALL is set), GPTMTAR and GPTMTAPS are updated according to the configuration of this bit.
0x0 = Update the GPTMTAR and GPTMTAV registers with the value in the GPTMTAILR register on the next cycle. Also update the GPTMTAPS register with the value in the GPTMTAPR register on the next cycle.
0x1 = Update the GPTMTAR and GPTMTAV registers with the value in the GPTMTAILR register on the next timeout. Also update the GPTMTAPS register with the value in the GPTMTAPR register on the next timeout.
|
| 7 |
TASNAPS |
R/W |
0x0 |
GPTM Timer A Snap-Shot Mode.
0x0 = Snap-shot mode is disabled.
0x1 = If Timer A is configured in the periodic mode, the actual free-running, capture or snapshot value of Timer A is loaded at the time-out event/capture or snapshot event into the GPTM Timer A (GPTMTAR) register. If the timer prescaler is used, the prescaler snapshot is loaded into the GPTM Timer A (GPTMTAPR).
|
| 6 |
TAWOT |
R/W |
0x0 |
GPTM Timer A Wait-on-Trigger.
If the application requires cyclical daisy-chaining, the TAWOT bit in the GPTMTAMR register of Timer 0 can be set.
In this case, Timer 0 waits for a trigger from the last timer module in the chain.
0x0 = Timer A begins counting as soon as it is enabled.
0x1 = If Timer A is enabled (TAEN is set in the GPTMCTL register), Timer A does not begin counting until it receives a trigger from the timer in the previous position in the daisy chain, see . This function is valid for one-shot, periodic, and PWM modes.
|
| 5 |
TAMIE |
R/W |
0x0 |
GPTM Timer A Match Interrupt Enable.
0x0 = The match interrupt is disabled for match events.Clearing the TAMIE bit in the GPTMTAMR register prevents assertion of µDMA or ADC requests generated on a match event. Even if the TATODMAEN bit is set in the GPTMDMAEV register or the TATOADCEN bit is set in the GPTMADCEV register, a µDMA or ADC match trigger is not sent to the µDMA or ADC, respectively, when the TAMIE bit is clear.
0x1 = An interrupt is generated when the match value in the GPTMTAMATCHR register is reached in the one-shot and periodic modes.
|
| 4 |
TACDIR |
R/W |
0x0 |
GPTM Timer A Count Direction.
When in PWM or RTC mode, the status of this bit is ignored.
PWM mode always counts down and RTC mode always counts up.
0x0 = The timer counts down.
0x1 = T he timer counts up. When counting up, the timer starts from a value of 0x0.
|
| 3 |
TAAMS |
R/W |
0x0 |
GPTM Timer A Alternate Mode Select.
0x0 = Capture or compare mode is enabled.
0x1 = PWM mode is enabled.To enable PWM mode, you must also clear the TACMR bit and configure the TAMR field to 0x1 or 0x2.
|
| 2 |
TACMR |
R/W |
0x0 |
GPTM Timer A Capture Mode.
0x0 = Edge-Count mode
0x1 = Edge-Time mode
|
| 1-0 |
TAMR |
R/W |
0x0 |
GPTM Timer A Mode.
The Timer mode is based on the timer configuration defined by bits
2:0 in the GPTMCFG register.
0x0 = Reserved
0x1 = One-Shot Timer mode
0x2 = Periodic Timer mode
0x3 = Capture mode
|