2.5.13 HFAULTSTAT Register (Offset = 0xD2C) [reset = 0x0]
Hard Fault Status (HFAULTSTAT)
NOTE
This register can only be accessed from privileged mode.
The HFAULTSTAT register gives information about events that activate the hard fault handler.
Bits are cleared by writing a 1 to them.
HFAULTSTAT is shown in Figure 2-25 and described in Table 2-38.
Return to Summary Table.
Figure 2-25 HFAULTSTAT Register
| 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
| DBG |
FORCED |
RESERVED |
| R/W-0x0 |
R/W1C-0x0 |
R-0x0 |
|
| 23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
| RESERVED |
| R-0x0 |
|
| 15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
| RESERVED |
| R-0x0 |
|
| 7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| RESERVED |
VECT |
RESERVED |
| R-0x0 |
R/W1C-0x0 |
R-0x0 |
|
Table 2-38 HFAULTSTAT Register Field Descriptions
| Bit |
Field |
Type |
Reset |
Description |
| 31 |
DBG |
R/W |
0x0 |
Debug Event
This bit is reserved for Debug use. This bit must be written as a 0, otherwise behavior is unpredictable.
|
| 30 |
FORCED |
R/W1C |
0x0 |
Forced Hard Fault
When this bit is set, the hard fault handler must read the other fault status registers to find the cause of the fault. This bit is cleared by writing a 1 to it.
|
| 29-2 |
RESERVED |
R |
0x0 |
|
| 1 |
VECT |
R/W1C |
0x0 |
Vector Table Read Fault
This error is always handled by the hard fault handler. When this bit is set, the PC value stacked for the exception return points to the instruction that was preempted by the exception. This bit is cleared by writing a 1 to it.
|
| 0 |
RESERVED |
R |
0x0 |
|