SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
Hibernation Data (HIBDATA)
This address space is implemented as a 16x32-bit memory (64 bytes). It can be loaded by the system processor in order to store state information and retains its state during a power cut operation as long as a battery is present. HIBDATA registers 0x050 to 0x064 (upper eight words) may only be accessed using the processor privileged mode (default).
NOTE
Except for the HIBIO and a portion of the HIBIC register, all other Hibernation module registers are on the Hibernation module clock domain and have special timing requirements. Software should make use of the WRC bit in the HIBCTL register to ensure that the required timing gap has elapsed. If the WRC bit is clear, any attempted write access is ignored. See Section 6.3.1. The HIBIO register and bits RSTWK, PADIOWK and WC of the HIBIC register do not require waiting for write to complete. Because these registers are clocked by the system clock, writes to these registers/bits are immediate.
Writing to registers other than the HIBCTL and HIBIM before the CLK32EN bit in the HIBCTL register has been set may produce unexpected results.
NOTE
If VDD is arbitrarily removed while a HIBDATA register write operation is in progress, the write operation must be retried after VDD is reapplied.
HIBDATA is shown in Figure 6-20 and described in Table 6-15.
Return to Summary Table.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
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