SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
When the Hibernation module has been configured and powered by an initial cold POR and is subsequently put into hibernation mode, a wake event (not including an external reset pin wake) causes the module to generate a system reset. This reset signal resets all circuitry on the device with the exception of the Hibernation module. All registers of the Hibernation module retain their values after this reset.
When the Hibernation module receives a wake event and VDD is enabled, a system reset sequence occurs: