6.5.5 HIBIM Register (Offset = 0x14) [reset = 0x0]
Hibernation Interrupt Mask (HIBIM)
This register is the interrupt mask register for the Hibernation module interrupt sources. Each bit in this register masks the corresponding bit in the Hibernation Raw Interrupt Status (HIBRIS) register. If a bit is unmasked, the interrupt is sent to the interrupt controller. If the bit is masked, the interrupt is not sent to the interrupt controller. The WC bit of the HIBIM register may be set before the CLK32EN bit of the HIBCTL register is set. This allows software to use the WC interrupt trigger to detect when the RTCOSC clock is stable, which may be in excess of one second. If the WC bit is set before the CLK32EN has been set, the mask value is not preserved over a hibernate cycle unless the bit is written a second time.
NOTE
The WC bit of this register is in the system clock domain such that a write to this bit is immediate and may be done before the CLK32EN bit is set in the HIBCTL register.
HIBIM is shown in Figure 6-13 and described in Table 6-8.
Return to Summary Table.
Figure 6-13 HIBIM Register
| 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
| RESERVED |
| R-0x0 |
|
| 23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
| RESERVED |
| R-0x0 |
|
| 15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
| RESERVED |
| R-0x0 |
|
| 7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| VDDFAIL |
RSTWK |
PADIOWK |
WC |
EXTW |
LOWBAT |
RESERVED |
RTCALT0 |
| R/W-0x0 |
R/W-0x0 |
R/W-0x0 |
R/W-0x0 |
R/W-0x0 |
R/W-0x0 |
R-0x0 |
R/W-0x0 |
|
Table 6-8 HIBIM Register Field Descriptions
| Bit |
Field |
Type |
Reset |
Description |
| 31-8 |
RESERVED |
R |
0x0 |
|
| 7 |
VDDFAIL |
R/W |
0x0 |
VDD Fail Interrupt Mask
0x0 = The VDDFAIL interrupt is suppressed and not sent to the interrupt controller.
0x1 = An interrupt is sent to the interrupt controller when the VDDFAIL bit in the HIBRIS register is set.
|
| 6 |
RSTWK |
R/W |
0x0 |
Reset Pad I/O Wake-Up Interrupt Mask
0x0 = The RSTWK interrupt is suppressed and not sent to the interrupt controller.
0x1 = An interrupt is sent to the interrupt controller when the RSTWK bit in the HIBRIS register is set.
|
| 5 |
PADIOWK |
R/W |
0x0 |
Pad I/O Wake-Up Interrupt Mask
0x0 = The PADIOWK interrupt is suppressed and not sent to the interrupt controller.
0x1 = An interrupt is sent to the interrupt controller when the PADIOWK bit in the HIBRIS register is set.
|
| 4 |
WC |
R/W |
0x0 |
External Write Complete/Capable Interrupt Mask
0x0 = The WC interrupt is suppressed and not sent to the interrupt controller.
0x1 = An interrupt is sent to the interrupt controller when the WC bit in the HIBRIS register is set.
|
| 3 |
EXTW |
R/W |
0x0 |
External Wake-Up Interrupt Mask
0x0 = The EXTW interrupt is suppressed and not sent to the interrupt controller.
0x1 = An interrupt is sent to the interrupt controller when the EXTW bit in the HIBRIS register is set.
|
| 2 |
LOWBAT |
R/W |
0x0 |
Low Battery Voltage Interrupt Mask
0x0 = The LOWBAT interrupt is suppressed and not sent to the interrupt controller.
0x1 = An interrupt is sent to the interrupt controller when the LOWBAT bit in the HIBRIS register is set.
|
| 1 |
RESERVED |
R |
0x0 |
|
| 0 |
RTCALT0 |
R/W |
0x0 |
RTC Alert 0 Interrupt Mask
0x0 = The RTCALT0 interrupt is suppressed and not sent to the interrupt controller.
0x1 = An interrupt is sent to the interrupt controller when the RTCALT0 bit in the HIBRIS register is set.
|