6.5.11 HIBIO Register (Offset = 0x2C) [reset = 0x80000000]
Hibernation IO Configuration (HIBIO)
This register is used to lock and unlock the external wake pin levels and enable the external RST pin and/or GPIO pins, Port K[7:4], as valid external WAKE sources.
NOTE
This register is in the system clock domain and does not require monitoring the WRC bit of the HIBCTL register before issuing a read or write of this register. Writes to this register are immediate.
NOTE
This register is in the core voltage domain and will not retain values over a hibernate cycle
HIBIO is shown in Figure 6-19 and described in Table 6-14.
Return to Summary Table.
Figure 6-19 HIBIO Register
| 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
| IOWRC |
RESERVED |
| R-0x1 |
R-0x0 |
|
| 23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
| RESERVED |
| R-0x0 |
|
| 15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
| RESERVED |
| R-0x0 |
|
| 7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| RESERVED |
WURSTEN |
RESERVED |
WUUNLK |
| R-0x0 |
R/W-0x0 |
R-0x0 |
R/W-0x0 |
|
Table 6-14 HIBIO Register Field Descriptions
| Bit |
Field |
Type |
Reset |
Description |
| 31 |
IOWRC |
R |
0x1 |
I/O Write Complete
Indicates whether or not the configuration that was programmed by the WURSTEN bit or GPIOWAKEPEN and GPIOWAKELVL registers have propagated through the pad ring.
0x0 = The changes programmed in the external pad I/O wake source registers have not propagated through the pad I/O.
0x1 = The changes programmed in the external pad I/O wake source registers have propagated through the pad I/O.
|
| 30-5 |
RESERVED |
R |
0x0 |
|
| 4 |
WURSTEN |
R/W |
0x0 |
Reset Wake Source Enable
This register bit programming takes affect after WUUNLK has been set.
0x0 = The RST signal is not enabled as a wake source.
0x1 = The RST signal is enabled as a wake source.
|
| 3-1 |
RESERVED |
R |
0x0 |
|
| 0 |
WUUNLK |
R/W |
0x0 |
I/O Wake Pad Configuration Enable
0x0 = The I/O WAKE configuration set by the WURSTEN bit or in the GPIO module registers GPIOWAKEPEN and GPIOWAKELVL is ignored.
0x1 = Implement the I/O WAKE configuration, level and enables for the external RST pin and/or GPIO wake-enabled pins.This bit must be cleared before issuing a hibernate request by setting the HIBREQ bit in the HIBCTL register.
|