SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
Hibernation RTC Match 0 (HIBRTCM0)
This register is the 32-bit seconds match register for the RTC counter. The 15-bit sub second match value is stored in the reading the RTCSSC field in the HIBRTCSS register and can be used in conjunction with this register for a more precise time match.
NOTE
Except for the HIBIO and a portion of the HIBIC register, all other Hibernation module registers are on the Hibernation module clock domain and have special timing requirements. Software should make use of the WRC bit in the HIBCTL register to ensure that the required timing gap has elapsed. If the WRC bit is clear, any attempted write access is ignored. See Section 6.3.1. The HIBIO register and bits RSTWK, PADIOWK and WC of the HIBIC register do not require waiting for write to complete. Because these registers are clocked by the system clock, writes to these registers/bits are immediate.
Writing to registers other than the HIBCTL and HIBIM before the CLK32EN bit in the HIBCTL register has been set may produce unexpected results.
HIBRTCM0 is shown in Figure 6-10 and described in Table 6-5.
Return to Summary Table.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RTCM0 | |||||||||||||||||||||||||||||||
| R/W-0xFFFFFFFF | |||||||||||||||||||||||||||||||