SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
The HIB Tamper Status (HIBTPCTL) register provides status of the module.
NOTE
Except for the HIBIO and a portion of the HIBIC register, all other Hibernation module registers are on the Hibernation module clock domain and have special timing requirements. Software should make use of the WRC bit in the HIBCTL register to ensure that the required timing gap has elapsed. If the WRC bit is clear, any attempted write access is ignored. See Section 6.3.1. The HIBIO register and bits RSTWK, PADIOWK and WC of the HIBIC register do not require waiting for write to complete. Because these registers are clocked by the system clock, writes to these registers/bits are immediate.
Writing to registers other than the HIBCTL and HIBIM before the CLK32EN bit in the HIBCTL register has been set may produce unexpected results.
NOTE
Errant writes to the Tamper registers are protected by the Hibernate HIBLOCK register.
HIBTPSTAT is shown in Figure 6-30 and described in Table 6-25.
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| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| R-0x0 | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| R-0x0 | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | |||||||
| R-0x0 | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | STATE | XOSCST | XOSCFAIL | ||||
| R-0x0 | R-0x0 | R-0x0 | R/W1C-0x0 | ||||