SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
In master mode, QSSI module can enable a high speed clock by setting the HSCLKEN bit in the SSI Control 1 (SSICR1) register. In this mode of operation, SSInCLK from the QSSI master operation is reflected back as a loopback clock, HSPEEDCLK, to the QSSI module. This allows faster timing since the logic can be used to adjust clock to external data relationships. HSPEEDCLK captures RX data in a separate register. This allows the time between the clock as seen by a remote device and the internal clock to match more closely.
Receive data is captured in a separate register sampled on loop-back clock (HSPEEDCLK) and the RX FIFO write control registered on HSPEEDCLK. If the HSCKEN = 1, the corresponding shift register and FIFO write enable will be selected for use. This supports faster QSSI master speed.
NOTE
For proper functionality of high speed mode, the HSCLKEN bit in the SSICR1 register should be set before any SSI data transfer or after applying a reset to the QSSI module. In addition, the SSE bit must be set to 0x1 before the HSCLKEN bit is set.