SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
The I2C peripheral has support for high-speed operation as both a master and slave. High-speed mode is configured by setting the HS bit in the I2C Master Control/Status (I2CMCS) register. High-speed mode transmits data at a high bit rate with a 66.6%/33.3% duty cycle, but communication and arbitration are done at standard, fast mode, or fast-mode plus speed, depending on which is selected by the user. When the HS bit in the I2CMCS register is set, current mode pullups are enabled.
The clock period can be selected using Equation 62, but in this case, SCL_LP = 2 and SCL_HP = 1.
For example:
Yields a SCL frequency of: 1 / T = 3.33 MHz
Table 19-2 gives examples of timer period and system clock in high-speed mode. Note that the HS bit in the I2CMTPR register must be set for the TPR value to be used in high-speed mode.
System Clock | Timer Period | Transmission Mode |
---|---|---|
40 MHz | 0x01 | 3.33 Mbps |
50 MHz | 0x02 | 2.77 Mbps |
80 MHz | 0x03 | 3.33 Mbps |
When operating as a master, the protocol is shown in Figure 19-7. The master is responsible for sending a master code byte in either standard (100 kbps) or fast mode (400 kbps) before it begins transferring in high-speed mode. The master code byte must contain data in the form of 0000.1XXX and is used to tell the slave devices to prepare for a high-speed transfer. The master code byte should never be acknowledged by a slave since it is only used to indicate that the upcoming data is going to be transferred at a higher data rate. To send the master code byte for a standard high-speed transfer, software should place the value of the master code byte into the I2CMSA register and write the I2CMCS register with a value of 0x13. If a high-speed burst transfer is required, then to send the master code byte, software should place the value of the master code byte into the I2CMSA register and write the I2CMCS register with 0x50. Either configuration places the I2C master peripheral in high-speed mode, and all subsequent transfers (until STOP) are carried out at high-speed data rate using the normal I2CMCS command bits, without setting the HS bit in the I2CMCS register. Again, setting the HS bit in the I2CMCS register is only necessary during the master code byte.
When operating as a high-speed slave, no additional software is required.
NOTE
High-Speed mode is 3.4 Mbps it the correct system clock frequency is set and there is appropriate pull strength on SCL and SDA lines.