SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
HSYNC (LCDLP signal) toggles after all pixels in a horizontal line have been transmitted to the LCD and a programmable number of pixel clock wait states have elapsed both at the beginning and end of each line. The LCD Raster Timing 0 (LCDRASTRTIM0) register, offset 0x02C, fully defines the behavior of this signal.
HSYNC can be programmed to be synchronized with the rising or falling edge of the pixel clock (LCDCP). The PXLCLKCTL and PSYNCRF bits in the LCD Raster Timing 2 (LCDRASTRTIM2) register, offset 0x034, are used to configure the synchronization.
The timings of the horizontal clock (line clock) pins are programmable to support: