SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
The I2C bus uses only two signals: SDA and SCL (named I2CSDA and I2CSCL on MSP432E4 microcontrollers). SDA is the bidirectional SDA and SCL is the bidirectional serial clock line. The bus is considered idle when both lines are high.
Every transaction on the I2C bus is nine bits long, consisting of eight data bits and a single acknowledge bit. The number of bytes per transfer (defined as the time between a valid START and STOP condition, described in Section 19.3.1.1) is unrestricted, but each data byte must be followed by an acknowledge bit, and data must be transferred MSB first. When a receiver cannot receive another complete byte, it can hold the clock line SCL low and force the transmitter into a wait state. The data transfer continues when the receiver releases the clock SCL.