| 31-12 |
RESERVED |
R |
0x0 |
|
| 11 |
RXFFIM |
R/W |
0x0 |
Receive FIFO Full Interrupt Mask
0x0 = The RXFFRIS interrupt is suppressed and not sent to the interrupt controller.
0x1 = The Receive FIFO Full interrupt is sent to the interrupt controller when the RXFFRIS bit in the I2CMRIS register is set.
|
| 10 |
TXFEIM |
R/W |
0x0 |
Transmit FIFO Empty Interrupt Mask. The TXFEIM interrupt mask bit in the I2CMIMR register should be clear (masking the TXFE interrupt) when the master is performing an RX Burst from the RXFIFO and should be unmasked before starting a TX FIFO transfers.
0x0 = The TXFERIS interrupt is suppressed and not sent to the interrupt controller.
0x1 = The Transmit FIFO Empty interrupt is sent to the interrupt controller when the TXFERIS bit in the I2CMRIS register is set.
|
| 9 |
RXIM |
R/W |
0x0 |
Receive FIFO Request Interrupt Mask
0x0 = The RXRIS interrupt is suppressed and not sent to the interrupt controller.
0x1 = The RX FIFO Request interrupt is sent to the interrupt controller when the RXRIS bit in the I2CMRIS register is set.
|
| 8 |
TXIM |
R/W |
0x0 |
Transmit FIFO Request Interrupt Mask
0x0 = The TXRIS interrupt is suppressed and not sent to the interrupt controller.
0x1 = The TX FIFO Request interrupt is sent to the interrupt controller when the TXRIS bit in the I2CMRIS register is set.
|
| 7 |
ARBLOSTIM |
R/W |
0x0 |
Arbitration Lost Interrupt Mask
0x0 = The ARBLOSTRIS interrupt is suppressed and not sent to the interrupt controller.
0x1 = The Arbitration Lost interrupt is sent to the interrupt controller when the ARBLOSTRIS bit in the I2CMRIS register is set.
|
| 6 |
STOPIM |
R/W |
0x0 |
STOP Detection Interrupt Mask
0x0 = The STOPRIS interrupt is suppressed and not sent to the interrupt controller.
0x1 = The STOP detection interrupt is sent to the interrupt controller when the STOPRIS bit in the I2CMRIS register is set.
|
| 5 |
STARTIM |
R/W |
0x0 |
START Detection Interrupt Mask
0x0 = The STARTRIS interrupt is suppressed and not sent to the interrupt controller.
0x1 = The START detection interrupt is sent to the interrupt controller when the STARTRIS bit in the I2CMRIS register is set.
|
| 4 |
NACKIM |
R/W |
0x0 |
Address/Data NACK Interrupt Mask
0x0 = The NACKRIS interrupt is suppressed and not sent to the interrupt controller.
0x1 = The address/data NACK interrupt is sent to the interrupt controller when the NACKRIS bit in the I2CMRIS register is set.
|
| 3 |
DMATXIM |
R/W |
0x0 |
Transmit DMA Interrupt Mask
0x0 = The DMATXRIS interrupt is suppressed and not sent to the interrupt controller.
0x1 = The transmit DMA complete interrupt is sent to the interrupt controller when the DMATXRIS bit in the I2CMRIS register is set.
|
| 2 |
DMARXIM |
R/W |
0x0 |
Receive DMA Interrupt Mask
0x0 = The DMARXRIS interrupt is suppressed and not sent to the interrupt controller.
0x1 = The receive DMA complete interrupt is sent to the interrupt controller when the DMARXRIS bit in the I2CMRIS register is set.
|
| 1 |
CLKIM |
R/W |
0x0 |
Clock Time-out Interrupt Mask
0x0 = The CLKRIS interrupt is suppressed and not sent to the interrupt controller.
0x1 = The clock timeout interrupt is sent to the interrupt controller when the CLKRIS bit in the I2CMRIS register is set.
|
| 0 |
IM |
R/W |
0x0 |
Master Interrupt Mask
0x0 = The RIS interrupt is suppressed and not sent to the interrupt controller.
0x1 = The master interrupt is sent to the interrupt controller when the RIS bit in the I2CMRIS register is set.
|