| 31-12 |
RESERVED |
R |
0x0 |
|
| 11 |
RXFFMIS |
R |
0x0 |
Receive FIFO Full Interrupt Mask. This bit is cleared by writing a 1 to the RXFFIC bit in the I2CMICR register.
0x0 = No interrupt.
0x1 = An unmasked Receive FIFO Full interrupt was signaled and is pending.
|
| 10 |
TXFEMIS |
R |
0x0 |
Transmit FIFO Empty Interrupt Mask. This bit is cleared by writing a 1 to the TXFEIC bit in the I2CMICR register.
0x0 = No interrupt.
0x1 = An unmasked Transmit FIFO Empty interrupt was signaled and is pending.
|
| 9 |
RXMIS |
R |
0x0 |
Receive FIFO Request Interrupt Mask. This bit is cleared by writing a 1 to the RXIC bit in the I2CMICR register.
0x0 = No interrupt.
0x1 = An unmasked Receive FIFO Request interrupt was signaled and is pending.
|
| 8 |
TXMIS |
R |
0x0 |
Transmit Request Interrupt Mask. This bit is cleared by writing a 1 to the TXIC bit in the I2CMICR register.
0x0 = No interrupt.
0x1 = An unmasked Transmit FIFO Request interrupt was signaled and is pending.
|
| 7 |
ARBLOSTMIS |
R |
0x0 |
Arbitration Lost Interrupt Mask. This bit is cleared by writing a 1 to the ARBLOSTIC bit in the I2CMICR register.
0x0 = No interrupt.
0x1 = An unmasked Arbitration Lost interrupt was signaled and is pending.
|
| 6 |
STOPMIS |
R |
0x0 |
STOP Detection Interrupt Mask. This bit is cleared by writing a 1 to the STOPIC bit in the I2CMICR register.
0x0 = No interrupt.
0x1 = An unmasked STOP Detection interrupt was signaled and is pending.
|
| 5 |
STARTMIS |
R |
0x0 |
START Detection Interrupt Mask. This bit is cleared by writing a 1 to the STARTIC bit in the I2CMICR register.
0x0 = No interrupt.
0x1 = An unmasked START Detection interrupt was signaled and is pending.
|
| 4 |
NACKMIS |
R |
0x0 |
Address/Data NACK Interrupt Mask. This bit is cleared by writing a 1 to the NACKIC bit in the I2CMICR register.
0x0 = No interrupt.
0x1 = An unmasked Address/Data NACK interrupt was signaled and is pending.
|
| 3 |
DMATXMIS |
R |
0x0 |
Transmit DMA Interrupt Status. This bit is cleared by writing a 1 to the DMATXIC bit in the I2CMICR register.
0x0 = No interrupt.
0x1 = An unmasked transmit DMA complete interrupt was signaled and is pending.
|
| 2 |
DMARXMIS |
R |
0x0 |
Receive DMA Interrupt Status. This bit is cleared by writing a 1 to the DMARXIC bit in the I2CMICR register.
0x0 = No interrupt.
0x1 = An unmasked receive DMA complete interrupt was signaled and is pending.
|
| 1 |
CLKMIS |
R |
0x0 |
Clock Time-out Masked Interrupt Status. This bit is cleared by writing a 1 to the CLKIC bit in the I2CMICR register.
0x0 = No interrupt.
0x1 = An unmasked clock timeout interrupt was signaled and is pending.
|
| 0 |
MIS |
R |
0x0 |
Masked Interrupt Status. This bit is cleared by writing a 1 to the IC bit in the I2CMICR register.
0x0 = An interrupt has not occurred or is masked.
0x1 = An unmasked master interrupt was signaled and is pending.
|