| 31-12 |
RESERVED |
R |
0x0 |
|
| 11 |
RXFFRIS |
R |
0x0 |
Receive FIFO Full Raw Interrupt Status. This bit is cleared by writing a 1 to the RXFFIC bit in the I2CMICR register.
0x0 = No interrupt
0x1 = The Receive FIFO Full interrupt is pending.
|
| 10 |
TXFERIS |
R |
0x0 |
Transmit FIFO Empty Raw Interrupt Status. This bit is cleared by writing a 1 to the TXFEIC bit in the I2CMICR register. Note that if we clear the TXFERIS interrupt (by setting the TXFEIC bit) when the TX FIFO is empty, the TXFERIS interrupt does not reassert even though the TX FIFO remains empty in this situation.
0x0 = No interrupt
0x1 = The Transmit FIFO Empty interrupt is pending.
|
| 9 |
RXRIS |
R |
0x0 |
Receive FIFO Request Raw Interrupt Status. This bit is cleared by writing a 1 to the RXIC bit in the I2CMICR register.
0x0 = No interrupt
0x1 = The trigger level for the RX FIFO has been reached or there is data in the FIFO and the burst count is zero. Thus, a RX FIFO request interrupt is pending.
|
| 8 |
TXRIS |
R |
0x0 |
Transmit Request Raw Interrupt Status. This bit is cleared by writing a 1 to the TXIC bit in the I2CMICR register.
0x0 = No interrupt
0x1 = The trigger level for the TX FIFO has been reached and more data is needed to complete the burst. Thus, a TX FIFO request interrupt is pending.
|
| 7 |
ARBLOSTRIS |
R |
0x0 |
Arbitration Lost Raw Interrupt Status. This bit is cleared by writing a 1 to the ARBLOSTIC bit in the I2CMICR register.
0x0 = No interrupt
0x1 = The Arbitration Lost interrupt is pending.
|
| 6 |
STOPRIS |
R |
0x0 |
STOP Detection Raw Interrupt Status This bit is cleared by writing a 1 to the STOPIC bit in the I2CMICR register.
0x0 = No interrupt
0x1 = The STOP Detection interrupt is pending.
|
| 5 |
STARTRIS |
R |
0x0 |
START Detection Raw Interrupt Status. This bit is cleared by writing a 1 to the STARTIC bit in the I2CMICR register.
0x0 = No interrupt
0x1 = The START Detection interrupt is pending.
|
| 4 |
NACKRIS |
R |
0x0 |
Address/Data NACK Raw Interrupt Status. This bit is cleared by writing a 1 to the NACKIC bit in the I2CMICR register.
0x0 = No interrupt
0x1 = The address/data NACK interrupt is pending.
|
| 3 |
DMATXRIS |
R |
0x0 |
Transmit DMA Raw Interrupt Status. This bit is cleared by writing a 1 to the DMATXIC bit in the I2CMICR register.
0x0 = No interrupt.
0x1 = The transmit DMA complete interrupt is pending.
|
| 2 |
DMARXRIS |
R |
0x0 |
Receive DMA Raw Interrupt Status. This bit is cleared by writing a 1 to the DMARXIC bit in the I2CMICR register.
0x0 = No interrupt.
0x1 = The receive DMA complete interrupt is pending.
|
| 1 |
CLKRIS |
R |
0x0 |
Clock Time-out Raw Interrupt Status. This bit is cleared by writing a 1 to the CLKIC bit in the I2CMICR register.
0x0 = No interrupt.
0x1 = The clock timeout interrupt is pending.
|
| 0 |
RIS |
R |
0x0 |
Master Raw Interrupt Status. This interrupt includes Master transaction completed and Next byte transfer request. This bit is cleared by writing a 1 to the IC bit in the I2CMICR register.
0x0 = No interrupt.
0x1 = A master interrupt is pending.
|