19.5.15 I2CSCSR Register (Offset = 0x804) [reset = 0x0]
I2C Slave Control/Status (I2CSCSR)
This register functions as a control register when written, and a status register when read.
I2CSCSR as a read-only status register is shown in Figure 19-31 and described in Table 19-21.
I2CSCSR as a write-only control register is shown in Figure 19-32 and described in Table 19-22.
Return to Summary Table.
Figure 19-31 I2CSCSR Register — Read-Only Status Register
| 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
| ACTDMARX |
ACTDMATX |
RESERVED |
| R-0x0 |
R-0x0 |
R-0x0 |
|
| 23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
| RESERVED |
| R-0x0 |
|
| 15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
| RESERVED |
| R-0x0 |
|
| 7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| RESERVED |
QCMDRW |
QCMDST |
OAR2SEL |
FBR |
TREQ |
RREQ |
| R-0x0 |
RC-0x0 |
RC-0x0 |
R-0x0 |
R-0x0 |
R-0x0 |
R-0x0 |
|
Table 19-21 I2CSCSR Register Field Descriptions — Read-Only Status Register
| Bit |
Field |
Type |
Reset |
Description |
| 31-3 |
ACTDMARX |
R |
0x0 |
DMA RX Active Status.
0x0 = DMA RX is not active
0x1 = DMA RX is active.
|
| 30 |
ACTDMATX |
R |
0x0 |
DMA TX Active Status.
0x0 = DMA TX is not active
0x1 = DMA TX is active.
|
| 5 |
QCMDRW |
RC |
0x0 |
Quick Command Read / Write This bit only has meaning when the QCMDST bit is set.
0x0 = Quick command was a write
0x1 = Quick command was a read
|
| 4 |
QCMDST |
RC |
0x0 |
Quick Command Status.
0x0 = The last transaction was a normal transaction or a transaction has not occurred.
0x1 = The last transaction was a Quick Command transaction.
|
| 3 |
OAR2SEL |
R |
0x0 |
OAR2 Address Matched. This bit gets reevaluated after every address comparison.
0x0 = Either the address is not matched or the match is in legacy mode.
0x1 = OAR2 address matched and ACKed by the slave.
|
| 2 |
FBR |
R |
0x0 |
First Byte Received. This bit is only valid when the RREQ bit is set and is automatically cleared when data has been read from the I2CSDR register. This bit is not used for slave transmit operations.
0x0 = The first byte has not been received.
0x1 = The first byte following the slave's own address has been received.
|
| 1 |
TREQ |
R |
0x0 |
Transmit Request.
0x0 = No outstanding transmit request.
0x1 = The I2C controller has been addressed as a slave transmitter and is using clock stretching to delay the master until data has been written to the I2CSDR register.
|
| 0 |
RREQ |
R |
0x0 |
Receive Request.
0x0 = No outstanding receive data.
0x1 = The I2C controller has outstanding receive data from the I2C master and is using clock stretching to delay the master until the data has been read from the I2CSDR register.
|
Figure 19-32 I2CSCSR Register — Write-Only Control Register
| 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
|
|
RESERVED |
|
|
R-0x0 |
|
| 23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
| RESERVED |
| R-0x0 |
|
| 15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
| RESERVED |
| R-0x0 |
|
| 7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| RESERVED |
RXFIFO |
TXFIFO |
DA |
| R-0x0 |
W-0x0 |
W-0x0 |
W-0x0 |
|
Table 19-22 I2CSCSR Register Field Descriptions — Write-Only Control Register
| Bit |
Field |
Type |
Reset |
Description |
| 31-3 |
RESERVED |
R |
0x0 |
|
| 2 |
RXFIFO |
W |
0x0 |
RX FIFO Enable.
0 = Disables RX FIFO
1 = Enables RX FIFO
|
| 1 |
TXFIFO |
W |
0x0 |
TX FIFO Enable.
0 = Disables TX FIFO
1 = Enables TX FIFO
|
| 0 |
DA |
W |
0x0 |
Device Active.
0 = Disables the I2C slave operation.
1 = Enables the I2C slave operation.
After this bit has been set, it should not be set again unless it has been cleared by writing a 0 or by a reset, otherwise transfer failures may occur.
|