SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
I2C Slave Data (I2CSDR)
This register contains the data to be transmitted when in the Slave Transmit state, and the data received when in the Slave Receive state. If the RXFIFO bit or TXFIFO bit are enabled in the I2CSCSR register, then this register is ignored and the data value being transferred from the FIFO is contained in the I2CFIFODATA register.
NOTE
Best practice recommends that an application should not switch between the I2CSDR register and TX FIFO or vice versa for successive transactions.
I2CSDR is shown in Figure 19-33 and described in Table 19-23.
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| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | DATA | ||||||||||||||||||||||||||||||
| R-0x0 | R/W-0x0 | ||||||||||||||||||||||||||||||