| 31-9 |
RESERVED |
R |
0x0 |
|
| 8 |
RXFFRIS |
R |
0x0 |
Receive FIFO Full Raw Interrupt Status. This bit is cleared by writing a 1 to the RXFFIC bit in the I2CSICR register.
0x0 = No interrupt
0x1 = The Receive FIFO Full interrupt is pending.
|
| 7 |
TXFERIS |
R |
0x0 |
Transmit FIFO Empty Raw Interrupt Status. This bit is cleared by writing a 1 to the TXFEIC bit in the I2CSICR register. Note that if the TXFERIS interrupt is cleared (by setting the TXFEIC bit) when the TX FIFO is empty, the TXFERIS interrupt does not reassert even though the TX FIFO remains empty in this situation.
0x0 = No interrupt
0x1 = The Transmit FIFO Empty interrupt is pending.
|
| 6 |
RXRIS |
R |
0x0 |
Receive FIFO Request Raw Interrupt Status. This bit is cleared by writing a 1 to the RXIC bit in the I2CSICR register.
0x0 = No interrupt
0x1 = The trigger value for the FIFO has been reached and a RX FIFO Request interrupt is pending.
|
| 5 |
TXRIS |
R |
0x0 |
Transmit Request Raw Interrupt Status. This bit is cleared by writing a 1 to the TXIC bit in the I2CSICR register.
0x0 = No interrupt
0x1 = The trigger value for the FIFO has been reached and a TX FIFO Request interrupt is pending.
|
| 4 |
DMATXRIS |
R |
0x0 |
Transmit DMA Raw Interrupt Status. This bit is cleared by writing a 1 to the DMATXIC bit in the I2CSICR register.
0x0 = No interrupt.
0x1 = A transmit DMA complete interrupt is pending.
|
| 3 |
DMARXRIS |
R |
0x0 |
Receive DMA Raw Interrupt Status. This bit is cleared by writing a 1 to the DMARXIC bit in the I2CSICR register.
0x0 = No interrupt.
0x1 = A receive DMA complete interrupt is pending.
|
| 2 |
STOPRIS |
R |
0x0 |
Stop Condition Raw Interrupt Status. This bit is cleared by writing a 1 to the STOPIC bit in the I2CSICR register.
0x0 = No interrupt.
0x1 = A STOP condition interrupt is pending.
|
| 1 |
STARTRIS |
R |
0x0 |
Start Condition Raw Interrupt Status. This bit is cleared by writing a 1 to the STARTIC bit in the I2CSICR register.
0x0 = No interrupt.
0x1 = A START condition interrupt is pending.
|
| 0 |
DATARIS |
R |
0x0 |
Data Raw Interrupt Status. This interrupt encompasses: (1) Slave transaction received, (2) Slave transaction requested, and (3) Next byte transfer request This bit is cleared by writing a 1 to the DATAIC bit in the I2CSICR register.
0x0 = No interrupt.
0x1 = Slave Interrupt is pending.
|