17.4 Initialization and Configuration

To configure the GPIO pins of a particular port, follow these steps:

1. Enable the clock to the port by setting the appropriate bits in the RCGCGPIO register, see Section 4.2.87. In addition, the SCGCGPIO and DCGCGPIO registers can be programmed in the same manner to enable clocking in Sleep and Deep-Sleep modes.
2. Set the direction of the GPIO port pins by programming the GPIODIR register. A write of a 1 indicates output and a write of a 0 indicates input.
3. Configure the GPIOAFSEL register to program each bit as a GPIO or alternate pin. If an alternate pin is chosen for a bit, then the PMCx field must be programmed in the GPIOPCTL register for the specific peripheral required. There are also two registers, GPIOADCCTL and GPIODMACTL, which can be used to program a GPIO pin as a ADC or μDMA trigger, respectively.
4. Set the EDMn field in the GPIOPC register as shown in Table 17-1.
5. Set or clear the GPIODR4R register bits as shown in Table 17-1.
6. Set or clear the GPIODR8R register bits as shown in Table 17-1.
7. Set or clear the GPIODR12R register bits as shown in Table 17-1.
8. Program each pad in the port to have either pullup, pulldown, or open drain functionality through the GPIOPUR, GPIOPDR, or GPIOODR register. Slew rate may also be programmed, if needed, through the GPIOSLR register.
9. To enable GPIO pins as digital I/Os, set the appropriate DEN bit in the GPIODEN register. To enable GPIO pins to their analog function (if available), set the GPIOAMSEL bit in the GPIOAMSEL register.
10. Program the GPIOIS, GPIOIBE, GPIOEV, and GPIOIM registers to configure the type, event, and mask of the interrupts for each port.

NOTE

To prevent false interrupts, the following steps should be taken when reconfiguring GPIO edge and interrupt sense registers:

1. Mask the corresponding port by clearing the IME field in the GPIOIM register.
2. Configure the IS field in the GPIOIS register and the IBE field in the GPIOIBE register.
3. Clear the GPIORIS register.
4. Unmask the port by setting the IME field in the GPIOIM register.
11. Optionally, software can lock the configurations of the NMI and JTAG/SWD pins on the GPIO port pins, by setting the LOCK bits in the GPIOLOCK register.

When the internal POR signal is asserted and until otherwise configured, all GPIO pins are configured to be undriven (tristate): GPIOAFSEL = 0, GPIODEN = 0, GPIOPDR = 0, and GPIOPUR = 0Table 17-2 shows all possible configurations of the GPIO pads and the control register settings required to achieve them. Table 17-3 shows how a rising edge interrupt is configured for pin 2 of a GPIO port.