SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
To use the WDT, its peripheral clock must be enabled by setting the Rn bit in the Watchdog Timer Run Mode Clock Gating Control (RCGCWD) register, see Section 4.2.85.
The Watchdog Timer is configured using the following sequence:
If software requires that all of the watchdog registers are locked, the Watchdog Timer module can be fully locked by writing any value to the WDTLOCK register. To unlock the Watchdog Timer, write a value of 0x1ACC.E551.
To service the watchdog, periodically reload the count value into the WDTLOAD register to restart the count. The interrupt can be enabled using the INTEN bit in the WDTCTL register to allow the processor to attempt corrective action if the watchdog is not serviced often enough. The RESEN bit in WDTCTL can be set so that the system resets if the failure is not recoverable using the ISR.
NOTE
The application should be sure not to modify the ALTCLK encoding in the ALTCLKCFG register while WDT1 is enabled and running.