2.5.3 INTCTRL Register (Offset = 0xD04) [reset = 0x0]
Interrupt Control and State (INTCTRL)
NOTE
This register can only be accessed from privileged mode.
The INCTRL register provides a set-pending bit for the NMI exception, and set-pending and clear-pending bits for the PendSV and SysTick exceptions. In addition, bits in this register indicate the exception number of the exception being processed, whether there are preempted active exceptions, the exception number of the highest priority pending exception, and whether any interrupts are pending.
When writing to INCTRL, the effect is unpredictable when writing a 1 to both the PENDSV and UNPENDSV bits, or writing a 1 to both the PENDSTSET and PENDSTCLR bits.
INTCTRL is shown in Figure 2-15 and described in Table 2-27.
Return to Summary Table.
Figure 2-15 INTCTRL Register
| 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
| NMISET |
RESERVED |
PENDSV |
UNPENDSV |
PENDSTSET |
PENDSTCLR |
RESERVED |
| R/W-0x0 |
R-0x0 |
R/W-0x0 |
W-0x0 |
R/W-0x0 |
W-0x0 |
R-0x0 |
|
| 23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
| ISRPRE |
ISRPEND |
RESERVED |
VECPEND |
| R-0x0 |
R-0x0 |
R-0x0 |
R-0x0 |
|
| 15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
| VECPEND |
RETBASE |
RESERVED |
| R-0x0 |
R-0x0 |
R-0x0 |
|
| 7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| VECACT |
| R-0x0 |
|
Table 2-27 INTCTRL Register Field Descriptions
| Bit |
Field |
Type |
Reset |
Description |
| 31 |
NMISET |
R/W |
0x0 |
NMI Set Pending
Because NMI is the highest-priority exception, normally the processor enters the NMI exception handler as soon as it registers the setting of this bit, and clears this bit on entering the interrupt handler. A read of this bit by the NMI exception handler returns 1 only if the NMI signal is reasserted while the processor is executing that handler.
|
| 30-29 |
RESERVED |
R |
0x0 |
|
| 28 |
PENDSV |
R/W |
0x0 |
PendSV Set Pending
Setting this bit is the only way to set the PendSV exception state to pending. This bit is cleared by writing a 1 to the UNPENDSV bit.
|
| 27 |
UNPENDSV |
W |
0x0 |
PendSV Clear Pending
This bit is write only; on a register read, its value is unknown.
|
| 26 |
PENDSTSET |
R/W |
0x0 |
SysTick Set Pending
This bit is cleared by writing a 1 to the PENDSTCLR bit.
|
| 25 |
PENDSTCLR |
W |
0x0 |
SysTick Clear Pending
This bit is write only; on a register read, its value is unknown.
|
| 24 |
RESERVED |
R |
0x0 |
|
| 23 |
ISRPRE |
R |
0x0 |
Debug Interrupt Handling
This bit is only meaningful in Debug mode and reads as zero when the processor is not in Debug mode.
|
| 22 |
ISRPEND |
R |
0x0 |
Interrupt Pending
This bit provides status for all interrupts excluding NMI and Faults.
|
| 21-20 |
RESERVED |
R |
0x0 |
|
| 19-12 |
VECPEND |
R |
0x0 |
Interrupt Pending Vector Number
This field contains the exception number of the highest priority pending enabled exception. The value indicated by this field includes the effect of the BASEPRI and FAULTMASK registers, but not any effect of the PRIMASK register.
|
| 11 |
RETBASE |
R |
0x0 |
Return to Base
This bit provides status for all interrupts excluding NMI and Faults. This bit only has meaning if the processor is currently executing an ISR (the Interrupt Program Status (IPSR) register is non-zero).
|
| 10-8 |
RESERVED |
R |
0x0 |
|
| 7-0 |
VECACT |
R |
0x0 |
Interrupt Pending Vector Number
This field contains the active exception number. The exception numbers can be found in the description for the VECPEND field. If this field is clear, the processor is in Thread mode. This field contains the same value as the ISRNUM field in the IPSR register. Subtract 16 from this value to obtain the IRQ number required to index into the Interrupt Set Enable (ENn), Interrupt Clear Enable (DISn), Interrupt Set Pending (PENDn), Interrupt Clear Pending (UNPENDn), and Interrupt Priority (PRIn) registers (see ).
|