SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
One interrupt for the DES is sent to the interrupt controller. This interrupt is an OR of the enabled interrupt bits in the DES Interrupt Status (DES_IRQSTATUS) register. These bits are enabled through the DES Interrupt Enable (DES_IRQENABLE) register. The following events can generate an interrupt bit to be set in the DES_IRQSTATUS register: