SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
Depending on the peripheral, the µDMA can indicate transfer completion at the end of an entire transfer or when a FIFO or buffer reaches a certain level ( Table 8-1 and the individual peripheral chapters). When a µDMA transfer is complete, a dma_done signal is sent to the peripheral that initiated the µDMA event. Interrupts can be enabled within the peripheral to trigger on µDMA transfer completion. For more information on peripheral µDMA interrupts, see the individual peripheral chapters. If the transfer uses the software µDMA channel, then the completion interrupt occurs on the dedicated software µDMA interrupt vector (see Table 8-5).
If the µDMA controller encounters a bus or memory protection error as it attempts to perform a data transfer, it disables the µDMA channel that caused the error and generates an interrupt on the µDMA error interrupt vector. The processor can read the DMA Bus Error Clear (DMAERRCLR) register to determine if an error is pending. The ERRCLR bit is set if an error occurred. The error can be cleared by writing a 1 to the ERRCLR bit.
Table 8-5 shows the dedicated interrupt assignments for the µDMA controller.
| Interrupt | Assignment |
|---|---|
| 44 | µDMA software channel transfer |
| 45 | µDMA error |