SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
The Hibernation module can generate interrupts when the following conditions occur:
All of the interrupts except for the tamper signals are ORed together before being sent to the interrupt controller, so the Hibernate module can only generate a single interrupt request to the controller at any given time. The software interrupt handler can service multiple interrupt events by reading the Hibernation Masked Interrupt Status (HIBMIS) register. Software can also read the status of the Hibernation module at any time by reading the HIBRIS register which shows all of the pending events. This register can be used after waking from hibernation to see if a wake condition was caused by one of the events above or by a power loss.
The WAKE pin can generate interrupts in Run, Sleep and Deep Sleep Mode. The events that can trigger an interrupt are configured by setting the appropriate bits in the Hibernation Interrupt Mask (HIBIM) register. Pending interrupts can be cleared by writing the corresponding bit in the Hibernation Interrupt Clear (HIBIC) register.