SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
Each pin of GPIO Port P and Port Q can trigger an interrupt. Each pin has a dedicated interrupt vector and can be handled by a separate interrupt handler. The PP0 and PQ0 interrupts serve as a master interrupt and provide a legacy aggregated interrupt version. For interrupt assignments, see .
NOTE
The OR'ed summary interrupt occurs on bit 0 of the GPIORIS register. For summary interrupt mode, software should set the GPIOIM register to 0xFF and mask the port pin interrupts 1 through 7 in the Interrupt Clear Enable (DISn) register (see Section 2.4). When servicing this interrupt, write a 1 to the corresponding bit in the UNPENDn register to clear the pending interrupt in the NVIC and clear the GPIORIS register pin interrupt bits by setting the IC field of the GPIOICR register to 0xFF.