SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
The JTAG port is composed of four pins: TCK, TMS, TDI, and TDO. Data is transmitted serially into the controller on TDI and out of the controller on TDO. The interpretation of this data is dependent on the current state of the TAP controller. For detailed information on the operation of the JTAG port and test access port (TAP) controller, see the IEEE Standard 1149.1-Test Access Port and Boundary-Scan Architecture.
The MSP432E4 JTAG controller works with the Arm® JTAG controller built into the Cortex®-M4F core by multiplexing the TDO outputs from both JTAG controllers. Arm JTAG instructions select the Arm TDO output while JTAG instructions select the TDO output. The multiplexer is controlled by the JTAG controller, which has comprehensive programming for the Arm core, MSP432E4 microcontroller, and unimplemented JTAG instructions.
The JTAG module has the following features:
See the Arm Debug Interface V5 Architecture Specification for more information on the Arm JTAG controller.