SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
This chapter describes the following peripherals:
Provides a simple, 24-bit clear-on-write, decrementing, wrap-on-zero counter with a flexible control mechanism.
Provides system implementation information and system control, including configuration, control, and reporting of system exceptions.
Supports the standard Armv7 Protected Memory System Architecture (PMSA) model. The MPU provides full support for protection regions, overlapping protection regions, access permissions, and exporting memory attributes to the system.
Fully supports single-precision add, subtract, multiply, divide, multiply and accumulate, and square root operations. It also provides conversions between fixed-point and floating-point data formats, and floating-point constant instructions.
Table 2-1 shows the address map of the Private Peripheral Bus (PPB). Some peripheral register regions are split into two address regions, as indicated by two addresses listed.
| Address | Core Peripheral | Description |
|---|---|---|
| 0xE000.E010 to 0xE000.E01F | System Timer | Section 2.2.1 |
| 0xE000.E100 to 0xE000.E4EF
0xE000.EF00 to 0xE000.EF03 |
Nested Vectored Interrupt Controller | Section 2.2.2 |
| 0xE000.E008-0xE000.E00F
0xE000.ED00 to 0xE000.ED3F |
System Control Block | Section 2.2.3 |
| 0xE000.ED90 to 0xE000.EDB8 | Memory Protection Unit | Section 2.2.4 |
| 0xE000.EF30 to 0xE000.EF44 | Floating Point Unit | Section 2.2.5 |