16.1 Introduction

The EPI has the following features:

• 8-, 16-, or 32-bit dedicated parallel bus for external peripherals and memory
• Memory interface supports contiguous memory access independent of data bus width, thus enabling code execution directly from synchronous dynamic random access memory (SDRAM), synchronous random access memory (SRAM), and flash memory
• Blocking and nonblocking reads
• Offloads the processor from the timing details of the parallel interface through use of an internal write FIFO
• Efficient transfers using Micro Direct Memory Access Controller (µDMA)
  • Separate channels for read and write
  • A read-channel request is asserted by programmable levels on the internal nonblocking read FIFO (NBRFIFO)
  • A write-channel request is asserted by empty on the internal write FIFO (WFIFO)

The EPI supports three primary functional modes: SDRAM mode, traditional host-bus mode, and general-purpose mode. The EPI module also provides a custom GPIO interface that enables fast parallel interfaces using a FIFO with speed control that uses an internal bit clock.

• SDRAM mode
  • Supports x16 (single data rate) SDRAM at up to 60 MHz
  • Supports low-cost SDRAMs up to 64MB (512 megabits)
  • Includes automatic refresh and access to all banks and rows
  • Includes a sleep or standby mode to keep contents active with minimal power draw
  • Multiplexed address/data interface for reduced pin count
• Host-bus mode
  • Traditional x8 and x16 MCU bus interface capabilities
  • Access to SRAM, NOR flash memory, and other devices, with up to 1MB of addressing in nonmultiplexed mode and 256MB in multiplexed mode (512MB in host-bus 16 mode with no byte selects)
  • Support for up to 512Mb PSRAM in quad chip select mode, with dedicated configuration register read and write enable
  • Support of both muxed and demuxed address and data
  • Access to a range of devices supporting the nonaddress FIFO x8 and x16 interface variant, with support for external FIFO (XFIFO) empty and full signals
  • Speed controlled, with read and write data wait-state counters
  • Support for read or write burst mode to host bus
  • Multiple chip select modes including single, dual, and quad chip selects, with and without ALE
  • External iRDY signal provided for stall capability of reads and writes
  • Manual chip-enable (or use extra address pins)
• General-purpose mode
  • Wide parallel interfaces for fast communications with CPLDs and FPGAs
  • Data widths up to 32 bits
  • Data rates up to 150 MB/second
  • Optional "address" sizes from 4 bits to 20 bits
  • Optional clock output, read/write strobes, framing (with counter-based size), and clock-enable input
• General parallel GPIO
  • 1 to 32 bits, FIFOed with speed control
  • Useful for custom peripherals or for digital data acquisition and actuator controls