8.1 Introduction
The µDMA controller provides the following features:
- Arm®PrimeCell® 32-channel configurable µDMA controller
- Support for memory-to-memory, memory-to-peripheral, and peripheral-to-memory in multiple transfer modes
- Basic for simple transfer scenarios
- Ping-pong for continuous data flow
- Scatter-gather for a programmable list of up to 256 arbitrary transfers initiated from a single request
- Highly flexible and configurable channel operation
- Independently configured and operated channels
- Dedicated channels for supported on-chip modules
- Flexible channel assignments
- One channel each for receive and transmit path for bidirectional modules
- Dedicated channel for software-initiated transfers
- Per-channel configurable priority scheme
- Optional software-initiated requests for any channel
- Two levels of priority
- Design optimizations for improved bus access performance between µDMA controller and the processor core
- µDMA controller access that is subordinate to core access
- RAM striping
- Peripheral bus segmentation
- Data sizes of 8, 16, and 32 bits
- Programmable transfer size in binary steps from 1 to 1024
- Source and destination address increment size of byte, halfword, word, or no increment
- Maskable peripheral requests
- Interrupt on transfer completion with a separate interrupt per channel