SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
The LCD DMA engine can output graphics data to constantly refresh the external LCD display, without burdening the CPU, through interrupts or a firmware timer. The DMA operates on one or two frame buffers, which are set up during initialization. Using two frame buffers (ping-pong buffers) enables the simultaneous operation of outputting the current video frame to the external display and updating the next video frame. The ping-pong buffering approach is preferred in most applications.
When the Raster controller is used, the LCD DMA engine reads data from a frame buffer and writes it to the input FIFO. The Raster controller requests data from the FIFO for frame refresh, so the DMA is used to keep the FIFO filled.
When the LIDD controller is used, the LCD DMA engine accesses the address or data registers of the LIDD controller. The following steps are needed to configure the DMA engine:
In addition, depending on whether the application is operating in LIDD mode or Raster mode, the LCDLIDDCTL or the LCDRASTRCTL register should be configured appropriately, along with all of the timing registers. To enable DMA transfers, write 1 to the DMAEN bit in the LCDLIDDCTL or the LCDEN bit in the LCDRASTRCTL register.
NOTE
When the LCD DMA is enabled, do not read or write the LCD registers for the base and ceiling addresses (LCDDMABAFB0, LCDDMACAFB0, LCDDMABAFB1, and LCDDMACAFB1) with the CPU.
To change any of these registers, disable the DMA (clear the DMAEN bit in the LCDLIDDCTL register or the LCDEN bit in the LCDRASTRCTL register), update the registers, and enable the LCD DMA again.