20.7.26 LCDCLKEN Register (Offset = 0x6C) [reset = 0x0]
LCD Clock Enable (LCDCLKEN)
This register contains the Clock enables for each major domain within the LCD.
LCDCLKEN is shown in Figure 20-41 and described in Table 20-35.
Return to Summary Table.
Figure 20-41 LCDCLKEN Register
| 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
| RESERVED |
| R-0x0 |
|
| 23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
| RESERVED |
| R-0x0 |
|
| 15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
| RESERVED |
| R-0x0 |
|
| 7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| RESERVED |
DMA |
LIDD |
CORE |
| R-0x0 |
R/W-0x0 |
R/W-0x0 |
R/W-0x0 |
|
Table 20-35 LCDCLKEN Register Field Descriptions
| Bit |
Field |
Type |
Reset |
Description |
| 31-3 |
RESERVED |
R |
0x0 |
|
| 2 |
DMA |
R/W |
0x0 |
DMA Clock Enable. Software Clock Enable for the LCD DMA
0x0 = Clock Disabled
0x1 = Clock Enabled
|
| 1 |
LIDD |
R/W |
0x0 |
LIDD Submodule Clock Enable. Software Clock Enable for the LIDD submodule (character displays). The LIDD submodule runs on the System Clock domain
0x0 = Clock Disabled
0x1 = Clock Enabled
|
| 0 |
CORE |
R/W |
0x0 |
LCD Core Clock Enable. Software Clock Enable for the LCD core, which encompasses the Raster Active Matrix and Passive Matrix logic. The Core runs on the System Clock domain.
0x0 = Clock Disabled
0x1 = Clock Enabled
|