20.7.27 LCDCLKRESET Register (Offset = 0x70) [reset = 0x0]
LCD Clock Resets (LCDCLKRESET)
This register contains the Software Resets for each major domain within the LCD.
LCDCLKRESET is shown in Figure 20-42 and described in Table 20-36.
Return to Summary Table.
Figure 20-42 LCDCLKRESET Register
| 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
| RESERVED |
| R-0x0 |
|
| 23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
| RESERVED |
| R-0x0 |
|
| 15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
| RESERVED |
| R-0x0 |
|
| 7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| RESERVED |
MAIN |
DMA |
LIDD |
CORE |
| R-0x0 |
R/W-0x0 |
R/W-0x0 |
R/W-0x0 |
R/W-0x0 |
|
Table 20-36 LCDCLKRESET Register Field Descriptions
| Bit |
Field |
Type |
Reset |
Description |
| 31-4 |
RESERVED |
R |
0x0 |
|
| 3 |
MAIN |
R/W |
0x0 |
Software Reset for the entire LCD module. This reset affects the L3 clk and lcd_clk domain.
0x0 = Reset Disabled
0x1 = Reset Enabled
|
| 2 |
DMA |
R/W |
0x0 |
Software Reset for the DMA submodule. This reset affects the L3 clk domain.
0x0 = Reset Disabled
0x1 = Reset Enabled
|
| 1 |
LIDD |
R/W |
0x0 |
Software Reset for the LIDD submodule (character displays). This reset affects the LIDD logic in the lcd_clk domain.
0x0 = Reset Disabled
0x1 = Reset Enabled
|
| 0 |
CORE |
R/W |
0x0 |
Software Reset for the Core, which encompasses the Raster Active Matrix and Passive Matrix logic. This reset affects the Core (active matrix and passive matrix raster mode) logic in the lcd_clk domain.
0x0 = Reset Disabled
0x1 = Reset Enabled
|