SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
LCD Control (LCDCTL)
The LCD Control (LCDCTL) register configures the mode, clock frequencies, and restart behavior of the LCD Controller.
LCDCTL is shown in Figure 20-17 and described in Table 20-9.
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31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0x0 | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0x0 | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
CLKDIV | |||||||
R/W-0x0 | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | LCDMODE | ||||||
R-0x0 | R/W-0x0 | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | 0x0 |
|
15-8 | CLKDIV | R/W | 0x0 |
Clock Divisor. This field contains a value (from 0 to 255) used to specify the frequency of the pixel clock, LCDCP (in Raster Mode) or MCLK (in LIDD mode). The equation for the two clock outputs is SYSCLK/CLKDIV, where: LCDCP can range from SYSCLK/2 to SYSCLK/255. CLKDIV = 0x0 or CLKDIV = 0x1 are not allowed. MCLK can vary from SYSCLK to SYSCLK/255 (using CLKDIV = 0x0 or CLKDIV = 0x1 sets MCLK = SYSCLK. See Table 20-10 for fSYSCLK to fLCDCP frequency conversions based on CLKDIV value. |
7-1 | RESERVED | R | 0x0 |
|
0 | LCDMODE | R/W | 0x0 |
LCD Mode Select. 0x0 = LCD Controller is operating in LIDD Mode 0x1 = LCD Controller is operating in Raster Mode |
fSYSCLK(MHz) | CLKDIV Value | fLCDCP(MHz) |
---|---|---|
120 | 2 | 60 |
3 | 40 | |
4 | 30 | |
5 | 24 | |
6 | 20 | |
7 | 17.1428 | |
8 | 15 | |
.. | .. | |
N | fSYSCLK/N | |
80 | 2 | 40 |
3 | 26.666 | |
4 | 20 | |
5 | 16 | |
6 | 13.333 | |
7 | 11.428 | |
.. | .. | |
N | fSYSCLK/N | |
60 | 2 | 30 |
3 | 20 | |
4 | 15 | |
5 | 12 | |
6 | 10 | |
N | fSYSCLK/N |