SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
LCD DMA Frame Buffer 0 Base Address (LCDDMABAFB0)
NOTE
When the LCD DMA is enabled, do not read or write the LCD registers for the base and ceiling addresses (LCDDMABAFB0, LCDDMACAFB0, LCDDMABAFB1, and LCDDMACAFB1) with the CPU. To change any of these registers, disable the DMA (clear the DMAEN bit in the LCDLIDDCTL register or the LCDEN bit in the LCDRASTRCTL register), update the registers, and enable the LCD DMA again.
LCDDMABAFB0 is shown in Figure 20-32 and described in Table 20-26.
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31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
FB0BA | |||||||
R/W-0x0 | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
FB0BA | |||||||
R/W-0x0 | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
FB0BA | |||||||
R/W-0x0 | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FB0BA | RESERVED | ||||||
R/W-0x0 | R-0x0 | ||||||