24-bit TFT mode packing.

This bit is only used when TFT24 and LCDTFT are both set to 1.

If TFT24UPCK is clear, 24-bit pixels are packed in 32-bit boundaries which means four pixels are saved in every three words, as shown below.

Word0: pix1[7:0], pix0[23:0]

Word1: pix2[15:0], pix1[23:8]

Word2: pix3[23:0], pix2[23:16]

See Figure 20-5 for information on how the pixels are packed.

If this bit is set to 1, then 24-bit pixels are stored unpacked in DDR with the uppermost byte unused, as shown below:

Word0: Unused[7:0], pix0[23:0]

Word1: Unused[7:0], pix1[23:0]

Word2: Unused[7:0], pix2[23:0]

Word3: Unused[7:0], pix3[23:0]

0x0 = 24-bit pixels are packed into 32 bit boundaries, which means 4 pixels are saved in every three words

0x1 = 24-bit pixels are stored unpacked in DDR with the uppermost byte unused

24-bit TFT mode.

0x0 = 24-Bit TFT Mode disabled. Palette RAM lookup is used for output pixel data.

0x1 = 24-Bit TFT Mode enabled. 24-bit data in TFT Active mode. The format of the framebuffer data depends on TFT24UPCK.

Frame buffer select.

This mode is valid when LCDTFT is 0 and there are 16 bpp raw data frame buffers (bpp= 00)

Only for this case, this bit selects whether the frame buffer format is 16 bpp 565 or 12bpp.

The Grayscaler can only take 12 bits per pixel. The frame buffer data is 16 bits per pixel 565 when FRMBUFSZ is set to 1 and only the 4 most significant bits of each color component are sent to the Grayscaler input.

0x0 = Framebuffer is 12 bpp packed in bits [11:0]

0x1 = Framebuffer is 16 bpp 565

TFT mode alternate signal mapping for palettized framebuffer.

This bit must be 0 for all 12-, 16-, or 24-bpp raw data formats. This bit must be 1 for 1-, 2-, 4-, or 8-bpp palette lookup data. Valid only in active matrix mode when LCDTFT = 1.

0x0 = 4 bits per component output data for 1-, 2-, 4-, and 8-bpp modes are right aligned on LCDDATA[11:0]

0x1 = 4 bits per component output data for 1-, 2-, 4-, and 8-bpp modes are converted to 5,6,5, format and use LCDDATA[15:0] = {R3 R2 R1 R0 R3 G3 G2 G1 G0 G3 G2 B3 B2 B1 B0 B3}

Nibble mode. This bit is used to determine palette indexing and is used in conjunction with RDORDER.

0x0 = Nibble mode is disabled

0x1 = Nibble mode is enabled

Pallette loading mode. For raw data (12, 16, or 24 bpp) frame buffers, no palette lookup is employed. Thus, these frame buffers use the data-only loading mode.

0x0 = Palette and data loading, reset value

0x1 = Palette loading only

0x2 = Data loading only

Palette loading delay.

This 8-bit parameter pauses reading of the Palette data from the asynchronous FIFO between each burst of 16 words. The delay is in terms of system clock (SYSCLK) cycles. The value (0-255) used to specify the number of system clock cycles that should be paused between bursts of 16 word reads from the asynchronous FIFO while loading the Palette SRAM. Programming REQDLY = 0x00 disables this pause when loading the Palette table.

When loading the Palette from system memory, palette data is burst into the internal Palette SRAM from the Asynchronous FIFO. 1, 2, and 4-bit per pixel frame buffer encodings use a fixed 16-word entry palette residing above the video data.

The 8-bit per pixel frame buffer encoding uses a 256-word entry palette residing above the video data. Likewise, 12, 16, and 24-bit per pixel frame buffer encodings also define a 256-word entry palette even though these encodings will not do a full bit-depth palette lookup. However, the 256-word palette entry must still be read from DDR as a frame buffer is fetched.

Bursting in 256 words in sequential SYSCLK cycles may cause the asynchronous FIFO to underflow depending on the DDR burst bandwidth.

Mono 8-bit.

This bit is ignored in all other modes.

0x0 = lcd_pixel_o[3:0] is used to output four pixel values to the panel each pixel clock transition

0x1 = lcd_pixel_o[7:0] is used to output eight pixel values to the panel each pixel clock transition.

Raster data order select.

For 1, 2, 4, and 8 BPP framebuffers. This bit has no effect on raw data framebuffers (12/16/24 bpp). This bit is used to determine palette indexing and is used in conjunction with NIBMODE.

0x0 = The framebuffer parsing for Palette Data lookup is from Bit 0 to bit 31 of the input word from the DMA output.

0x1 = The famebuffer parsing for Palette Data lookup is from Bit 31 to Bit 0 of the input word from the DMA output.

LCD TFT

0x0 = Passive or STN display operation enabled; dither logic is enabled.

0x1 = Active or TFT display operation enabled, external palette and DAC required, dither logic bypassed, pin timing changes to support continuous pixel clock, output enable, vsync, and hsync.

LCD monochrome. Only applies for passive matrix panels.

0x0 = Color operation enabled

0x1 = Monochrome operation enabled

LCD controller enable for raster operations.

This bit does not affect LIDD mode behavior.

0x0 = LCD controller disabled

0x1 = LCD controller enabled