SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
LCD Raster Timing 0 (LCDRASTRTIM0)
LCDRASTRTIM0 is shown in Figure 20-26 and described in Table 20-20.
Return to Summary Table.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
HBP | |||||||
R/W-0x0 | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
HFP | |||||||
R/W-0x0 | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
HSW | PPL | ||||||
R/W-0x0 | R/W-0x0 | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PPL | MSBPPL | RESERVED | |||||
R/W-0x0 | R/W-0x0 | R-0x0 | |||||