| 31 |
RESERVED |
R |
0x0 |
|
| 30-27 |
HSW |
R/W |
0x0 |
Bits 9:6 of the horizontal sync width field.
|
| 26 |
MSBLPP |
R/W |
0x0 |
MSB of lines per panel.
Bit 10 of the LPP field in LCDRASTRTIM1.
|
| 25 |
PXLCLKCTL |
R/W |
0x0 |
HSYNC/VSYNC pixel clock control on/off.
This bit MUST be programmed to 0 for passive matrix displays. The edge timing is fixed.
0x0 = LCDLP and LCDFP are driven on opposite edges of pixel clock than the LCD pixel output.
0x1 = LCDLP and LCDFP are driven according to bit 24, PSYNCRF
|
| 24 |
PSYNCRF |
R/W |
0x0 |
Program HSYNC/VSYNC rise or fall.
0x0 = LCDLP and LCDFP are driven on the falling edge of pixel clock (PXLCLKCTL must be set to 1).
0x1 = LCDLP and LCDFP are driven on the rising edge of pixel clock (PXLCLKCTL must be set to 1).
|
| 23 |
INVOE |
R/W |
0x0 |
Invert output enable.
Active display mode: data driven out of the LCD data lines on programmed pixel clock edge where AC-bias is active.
Passive display mode: INVOE is ignored.
0x0 = LCDAC pin is active high in active display mode
0x1 = LCDAC pin is active low in active display mode
|
| 22 |
INVPXLCLK |
R/W |
0x0 |
Invert pixel clock.
For active matrix output (LCDTFT = 1), the output pixel clock is a free running clock in that it transitions in horizontal blanking (including horizontal front porch, horizontal back porch) areas and all vertical blanking times.
For Passive Matrix output (LCDTFT = 0), the output pixel clock on occurs when an output data value is written. It is in a return-to-zero state when INVPXLCLK = 0 and a return-to-one state when INVPXLCLK = 1.
0x0 = Data is driven on the LCD data lines on the rising edge of LCDCP.
0x1 = Data is driven on the LCD data lines in the falling edge of LCDCP.
|
| 21 |
IHS |
R/W |
0x0 |
Invert hysync.
Active and passive mode: horizontal sync pulse/line clock active between lines, after the end of line wait period.
0x0 = LCDLP pin is active high and inactive low
0x1 = LCDLP pin is active low and inactive high
|
| 20 |
IVS |
R/W |
0x0 |
Invert vsync.
Active mode: vertical sync pulse active between frames, after end of frame wait period.
Passive mode: frame clock active during first line of each frame.
0x0 = LCDFP pin is active high and inactive low
0x1 = LCDFP pin is active low and inactive high
|
| 19-16 |
ACBI |
R/W |
0x0 |
AC bias pins transitions per interrupt.
Value (from 0x0 to 0xF) used to specify the number of AC Bias pin transitions to count before setting the line count status (ACBS) bit, signaling an interrupt request. Counter frozen when ACBS is set, and is restarted when ACBS is cleared by software. This function is disabled when ACBI = 0x0000.
|
| 15-8 |
ACBF |
R/W |
0x0 |
AC bias pin frequency.
Value (from 0x0 to 0xFF) used to specify the number of line clocks to count before transitioning the AC Bias pin. This pin is used to periodically invert the polarity of the power supply to prevent DC charge build-up within the display. ACBF = Number of line clocks/toggle of the LCDAC pin.
|
| 7-6 |
RESERVED |
R |
0x0 |
|
| 5-4 |
MSBHBP |
R/W |
0x0 |
Bits 9:8 of the horizontal back porch field.
|
| 3-2 |
RESERVED |
R |
0x0 |
|
| 1-0 |
MSBHFP |
R/W |
0x0 |
Bits 9:8 of the horizontal front porch field.
|