4.2.28 LDODPCAL Register (Offset = 0x1C0) [reset = 0x1212]
LDO Deep-Sleep Power Calibration (LDODPCAL)
This register provides factory determined values that are recommended for the VLDO field in the LDODPCTL register while in deep-sleep mode. The reset value of this register cannot be determined until the product has been characterized.
LDODPCAL is shown in Figure 4-34 and described in Table 4-41.
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Figure 4-34 LDODPCAL Register
| 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| RESERVED |
NOPLL |
30KHZ |
| R-0x0 |
R-0x12 |
R-0x12 |
|
Table 4-41 LDODPCAL Register Field Descriptions
| Bit |
Field |
Type |
Reset |
Description |
| 31-16 |
RESERVED |
R |
0x0 |
|
| 15-8 |
NOPLL |
R |
0x12 |
Deep-Sleep Without PLL.
The value in this field is the suggested value for the VLDO field in the LDODPCTL register when not using the PLL. This value provides the lowest recommended LDO output voltage for use with the system clock. |
| 7-0 |
30KHZ |
R |
0x12 |
Deep-Sleep With IOSC.
The value in this field is the suggested value for the VLDO field in the LDODPCTL register when not using the PLL. This value provides the lowest recommended LDO output voltage for use with the low-frequency internal oscillator. |