4.2.27 LDODPCTL Register (Offset = 0x1BC) [reset = 0x12]
LDO Deep-Sleep Power Control (LDODPCTL)
This register specifies the LDO output voltage in sleep mode. This register should be configured while in run mode. If the VADJEN bit is set, writes can be made to the VLDO field within the provided encodings. The following table shows the maximum clock frequencies with respect to LDO Voltage.
LDODPCTL is shown in Figure 4-33 and described in Table 4-40.
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Figure 4-33 LDODPCTL Register
| 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
| VADJEN |
RESERVED |
| R/W-0x0 |
R-0x0 |
|
| 23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
| RESERVED |
| R-0x0 |
|
| 15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
| RESERVED |
| R-0x0 |
|
| 7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| VLDO |
| R/W-0x12 |
|
Table 4-40 LDODPCTL Register Field Descriptions
| Bit |
Field |
Type |
Reset |
Description |
| 31 |
VADJEN |
R/W |
0x0 |
Voltage Adjust Enable.
This bit enables the value of the VLDO field to be used to specify the output voltage of the LDO in deep-sleep mode.
0x0 = The LDO output voltage is set to the factory default value in deep-sleep mode. The value of the VLDO field does not affect the LDO operation.
0x1 = The LDO output value in deep-sleep mode is configured by the value in the VLDO field.
|
| 30-8 |
RESERVED |
R |
0x0 |
|
| 7-0 |
VLDO |
R/W |
0x12 |
LDO Output Voltage.
This field provides program control of the LDO output voltage in deep-sleep mode. The value of the field is only used for the LDO voltage when the VADJEN bit is set.
0x12 = 0.90 V
0x13 = 0.95 V
0x14 = 1.00 V
0x15 = 1.05 V
0x16 = 1.10 V
0x17 = 1.15 V
0x18 = 1.20 V
All other values are reserved.
|