4.2.26 LDOSPCAL Register (Offset = 0x1B8) [reset = 0x1818]
LDO Sleep Power Calibration (LDOSPCAL)
This register provides factory determined values that are recommended for the VLDO field in the LDOSPCTL register while in sleep mode. The reset value of this register cannot be determined until the product has been characterized.
LDOSPCAL is shown in Figure 4-32 and described in Table 4-39.
Return to Summary Table.
Figure 4-32 LDOSPCAL Register
| 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| RESERVED |
WITHPLL |
NOPLL |
| R-0x0 |
R-0x18 |
R-0x18 |
|
Table 4-39 LDOSPCAL Register Field Descriptions
| Bit |
Field |
Type |
Reset |
Description |
| 31-16 |
RESERVED |
R |
0x0 |
|
| 15-8 |
WITHPLL |
R |
0x18 |
Sleep with PLL.
The value in this field is the suggested value for the VLDO field in the LDOSPCTL register when using the PLL. This value provides the lowest recommended LDO output voltage for use with the PLL at the maximum specified value. |
| 7-0 |
NOPLL |
R |
0x18 |
Sleep without PLL.
The value in this field is the suggested value for the VLDO field in the LDOSPCTL register when not using the PLL. This value provides the lowest recommended LDO output voltage for use without the PLL. |