4.2.25 LDOSPCTL Register (Offset = 0x1B4) [reset = 0x18]
LDO Sleep Power Control (LDOSPCTL)
This register specifies the LDO output voltage in sleep mode. This register should be configured while in run mode. If the VADJEN bit is set, writes can be made to the VLDO field within the provided encodings. Table 4-37 lists the maximum clock frequencies with respect to LDO voltage.
Table 4-37 Maximum System Clock and PIOSC Frequency with Respect to LDO Voltage
| Operating Voltage (LDO) |
Maximum System Clock Frequency |
PIOSC |
| 1.2 V |
120 MHz |
16 MHz |
| 0.9 V |
30 MHz |
16 MHz |
LDOSPCTL is shown in Figure 4-31 and described in Table 4-38.
Return to Summary Table.
Figure 4-31 LDOSPCTL Register
| 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
| VADJEN |
RESERVED |
| R/W-0x0 |
R-0x0 |
|
| 23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
| RESERVED |
| R-0x0 |
|
| 15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
| RESERVED |
| R-0x0 |
|
| 7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| VLDO |
| R/W-0x18 |
|
Table 4-38 LDOSPCTL Register Field Descriptions
| Bit |
Field |
Type |
Reset |
Description |
| 31 |
VADJEN |
R/W |
0x0 |
Voltage Adjust Enable.
This bit enables the value of the VLDO field to be used to specify the output voltage of the LDO in sleep mode.
0x0 = The LDO output voltage is set to the factory default value in sleep mode. The value of the VLDO field does not affect the LDO operation.
0x1 = The LDO output value in sleep mode is configured by the value in the VLDO field.
|
| 30-8 |
RESERVED |
R |
0x0 |
|
| 7-0 |
VLDO |
R/W |
0x18 |
LDO Output Voltage.
This field provides program control of the LDO output voltage in sleep mode. The value of the field is used only for the LDO voltage when the VADJEN bit is set. When using the USB module, the LDO must be configured to 1.2 V.
0x12 = 0.90 V
0x13 = 0.95 V
0x14 = 1.00 V
0x15 = 1.05 V
0x16 = 1.10 V
0x17 = 1.15 V
0x18 = 1.20 V
All other values are reserved.
|