| 31-27 |
WRSU |
R/W |
0x0 |
Write strobe (WR) setup cycles.
When performing a write access, this field defines the number of MCLK cycles that the LCDDATA bus, output enable, ADE, DIR and CS0 signals have to be ready before the write strobe. The minimum value is 0x0.
|
| 26-21 |
WRDUR |
R/W |
0x2 |
Write strobe (WR) duration cycles.
This field value defines the number of MCLK cycles for which the write strobe is held active when performing a write access. The minimum value is 0x1.
|
| 20-17 |
WRHOLD |
R/W |
0x2 |
Write strobe (WR) hold cycles.
This field value defines the number of MCLK cycles for which the LCDDATA bus, output enable, ALE, DIR and CS0 signals are held after the write strobe is deasserted when performing a write access. The minimum value is 0x1.
|
| 16-12 |
RDSU |
R/W |
0x0 |
Read strobe (RD) setup cycles.
When performing a read access, this field defines the number of MCLK cycles that the LCDDATA bus, output enable, ALE, DIR and CS0 signals have to be ready before the read strobe is asserted.
|
| 11-6 |
RDDUR |
R/W |
0x1 |
Read strobe (RD) duration cycles.
This field defines the number of MCLK cycles for which the read strobe is held active when performing a read access. The minimum value is 0x1.
|
| 5-2 |
RDHOLD |
R/W |
0x1 |
Read strobe (RD) hold cycles.
This field defines of MCLK cycles for which the LCDDATA bus, output enable, ALE, DIR and CS0 signals are held after the read strobe is deasserted when performing a read access. The minimum value is 0x1.
|
| 1-0 |
GAP |
R/W |
0x0 |
Field value defines the number of LCDMCLK cycles (GAP +1) between the end of one CS0 (LCDAC) device access and the start of another CS0 (LCDAC) device access unless the two accesses are both reads. In this case, this delay is not incurred. The minimum value is 0x0.
|