| 31-27 |
WRSU |
R/W |
0x0 |
Write strobe (WR) setup cycles.
When performing a write access, this field defines the number of LCDMCLK cycles that Data Bus/Pad Output Enable, ALE, DIR, and CS1 have to be ready before WR (LCDLP) is asserted. The minimum value is 0x0.
|
| 26-21 |
WRDUR |
R/W |
0x2 |
Write strobe (WR) duration cycles.
Field value defines the number of LCDMCLK cycles for which WR (LCDLP) is held active when performing a write access. The minimum value is 0x1.
|
| 20-17 |
WRHOLD |
R/W |
0x2 |
Write strobe (WR) hold cycles.
Field value defines the number of LCDMCLK cycles for which Data Bus/Pad Output Enable, ALE, the DIR, and CS1 signals are held after WR (LCDLP) is deasserted when performing a write access. The minimum value is 0x1.
|
| 16-12 |
RDSU |
R/W |
0x0 |
Read strobe (RD) setup cycles.
When performing a read access, this field defines the number of LCDMCLK cycles that Data Bus/Pad Output Enable, ALE, the DIR, and CS1 signals have to be ready before RD (LCDCP) is asserted.
|
| 11-6 |
RDDUR |
R/W |
0x1 |
Read strobe (RD) duration cycles.
Field value defines the number of LCDMCLK cycles for which RD (LCDCP) is held active when performing a read access. The minimum value is 0x1.
|
| 5-2 |
RDHOLD |
R/W |
0x1 |
Read strobe (RD) hold cycles.
Field value defines the number of LCDMCLK cycles for which Data Bus/Pad Output Enable, ALE, DIR, and CS1 signals are held after RD (LCDCP) is deasserted when performing a read access. The minimum value is 0x1.
|
| 1-0 |
GAP |
R/W |
0x0 |
Field value defines the number of LCDMCLK cycles (GAP + 1) between the end of one CS1 (LCDAC) device access and the start of another CS0 (LCDAC) device access unless the two accesses are both reads. In this case, this delay is not incurred. The minimum value is 0x0.
|