27.3.5.2 LPM Operation as a Host

When operating as a host, the USB initiates an LPM Suspend (transition from the L0 state to the L1 state) by initiating an LPM transaction as follows:

• Software configures the desired attributes of the Suspend in the USBLPMATTR register. Setting the RMTWAK bit and programming a large HIRD gives the peripheral more opportunity to conserve power.
• All LPM interrupts should be enabled in the USB LPM Interrupt Mask (USBLPMIM) register.
• Software should initiate the transaction by setting the TXLPM bit in the USBLPMCNTRL register.
• An interrupt is generated to inform software of the response to the LPM transaction. If an ACK was received then the USB suspends automatically within 8 µs. This is the indication that the USB has suspended.

If the response from the device has a bit-stuff error or a PID error, then the ERR bit is set in the USBLPMRIS register and an interrupt is generated. The hardware immediately attempts the LPM transaction two more times The device does not suspend for 8 µs after the initial LPM so it is able to respond to either of these subsequent LPM transactions. If an LPM timeout has occurred three times, the NC and the ERR interrupt bits are be set. At this time, software is unaware of the device state and must deduce it by other means.

Resume signaling should be generated by software as follows:

• All LPM interrupts should be enabled in the USBLPMIM register.
• Software should write the RES bit in the USBLPMCNTRL register. This bit is self-clearing and causes the resume signalling to be generated on the bus for the time that is currently specified in the HIRD field of the USBLPLMATTR register. It is assumed by hardware that this value was used in the last LPM transaction that caused the Suspend.
• After HIRD + 10 µs, the USB transitions to its normal operational state and is ready for packet transmissions. The RES bit is set in the USBLPMRIS register and a interrupt may be generated.

If the remote wakeup feature was enabled in the LPM transaction that caused the Suspend, then the device may drive resume signaling on the bus. When this occurs, the device drives resume signaling on the bus for 50 µs. The USB host immediately begins driving resume signaling on the bus and does so for 60 µs. 10 µs after completion of the resume signaling, the USB transitions to its normal operating state and is ready for packet transmission. At this time, the RES interrupt bit is set in the USBLPMRIS register and an interrupt may be generated.