SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
Flow control mechanisms can be enabled for both the TX and RX FIFO data path, depending on the configurations in the Ethernet MAC Flow Control (EMACFLOWCTL) register at offset 0x018 and the DUPM bit configuration in the Ethernet MAC Configuration (EMACCFG) register at offset 0x000.
| TFE Bit in EMACFLOWCTL | DUPM Bit in EMACCFG | Description |
|---|---|---|
| 0 | X | The MAC transmitter does not perform the flow control or backpressure operation. |
| 1 | 0 | The MAC transmitter performs backpressure when the FCBBPA bit in the Ethernet MAC Flow Control (EMACFLOWCTL) register is set. |
| 1 | 1 | The MAC transmitter sends a pause frame when the FCBBPA bit in the Ethernet MAC Flow Control (EMACFLOWCTL) register is set. |
| TFE Bit in EMACFLOWCTL | DUPM Bit in EMACCFG | Description |
|---|---|---|
| 0 | X | The MAC receiver does not detect the received Pause frames. |
| 1 | 0 | The MAC receiver does not detect the received Pause frames but recognizes such frames as Control frames. |
| 1 | 1 | The MAC receiver detects or processes the Pause frames and responds to such frames by stopping the MAC transmitter. |