SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
The MAC Management Counters (MMC) module maintains a set of registers for gathering statistics on the received and transmitted frames. The register set includes a control register for controlling the behavior of the registers, two 32-bit registers containing interrupts generated (one for receive and one for transmit), and two 32-bit registers containing masks for the Interrupt register (one for receive and one for transmit). The MMC counters are free running and start counting when a corresponding frame is received or transmitted. The MMC counter registers provided are as follows: