SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
This section describes the Memory protection unit (MPU). The MPU divides the memory map into a number of regions and defines the location, size, access permissions, and memory attributes of each region. The MPU supports independent attribute settings for each region, overlapping regions, and export of memory attributes to the system.
The memory attributes affect the behavior of memory accesses to the region. The Cortex-M4 MPU defines eight separate memory regions, 0 to 7, and a background region.
When memory regions overlap, a memory access is affected by the attributes of the region with the highest number. For example, the attributes for region 7 take precedence over the attributes of any region that overlaps region 7.
The background region has the same memory access attributes as the default memory map, but is accessible from privileged software only.
The Cortex-M4 MPU memory map is unified, meaning that instruction accesses and data accesses have the same region settings.
If a program accesses a memory location that is prohibited by the MPU, the processor generates a memory management fault, causing a fault exception and possibly causing termination of the process in an OS environment. In an OS environment, the kernel can update the MPU region setting dynamically based on the process to be executed. Typically, an embedded OS uses the MPU for memory protection.
Configuration of MPU regions is based on memory types. For more information, see Section 1.5.1.
Table 2-2 shows the possible MPU region attributes. For programming a microcontroller implementation, see Section 2.2.4.2.1 for guidelines.
| Memory Type | Description |
|---|---|
| Strongly Ordered | All accesses to strongly ordered memory occur in program order. |
| Device | Memory-mapped peripherals |
| Normal | Normal memory |
To avoid unexpected behavior, disable the interrupts before updating the attributes of a region that the interrupt handlers might access.
Ensure software uses aligned accesses of the correct size to access MPU registers:
The processor does not support unaligned accesses to MPU registers.
When setting up the MPU, and if the MPU has previously been programmed, disable unused regions to prevent any previous region settings from affecting the new MPU setup.