SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
Memory Timing Parameter Register 0 for Main Flash and EEPROM (MEMTIM0)
The MEMTIM0 register provides timing parameters for the main Flash and EEPROM memories. The timing parameters apply to the memory while the system is in run or sleep mode; the clocking for these modes is consistent and unchanged, because the system clock frequency and source remains unchanged during transitions between run-to-sleep and sleep-back-to-run. Writes to MEMTIM0 do not have any effect on system state; the register contents are applied only when the MEMTIMU bit in the RSCLKCFG register is set. Doing so allows the software to execute out of the same memory system for which the timing parameters are being modified.
Depending on the CPU frequency, the application must program specific values into the fields of the MEMTIM0 register. Table 4-22 details the bit field values that are required for the given CPU frequency ranges.
| CPU Frequency Range (f) in MHz | Time Period Range (t) in ns | FBCHT and EBCHT | FBCE and EBCE | FWS and EWS |
|---|---|---|---|---|
| 16 | 62.5 | 0x0 | 1 | 0x0 |
| 16 < f ≤ 40 | 62.5 > t ≥ 25 | 0x2 | 0 | 0x1 |
| 40 < f ≤60 | 25 > t ≥ 16.67 | 0x3 | 0 | 0x2 |
| 60 < f ≤ 80 | 16.67 > t ≥ 12.5 | 0x4 | 0 | 0x3 |
| 80 < f ≤ 100 | 12.5 > t ≥ 10 | 0x5 | 0 | 0x4 |
| 100 < f ≤ 120 | 10 > t ≥ 8.33 | 0x6 | 0 | 0x5 |
NOTE
The associated flash and EEPROM fields in the MEMTIM0 register must be programmed to the same values. For example, the FWS field must be programmed to the same value as the EWS field.
MEMTIM0 is shown in Figure 4-18 and described in Table 4-23.
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| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | EBCHT | ||||||
| R-0x0 | R/W-0x0 | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| EBCHT | EBCE | RESERVED | EWS | ||||
| R/W-0x0 | R/W-0x1 | R-0x0 | R/W-0x0 | ||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | FBCHT | ||||||
| R/W-0x0 | R/W-0x0 | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| FBCHT | FBCE | RESERVED | FWS | ||||
| R/W-0x0 | R/W-0x1 | R/W-0x1 | R/W-0x0 | ||||