SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
The MAC Module has the capability of providing an MII or RMII depending on the interface selected in the Ethernet MAC Peripheral Configuration (EMACPC) register, at offset 0xFC4. Except for EN0RREF_CLK, the signals used for RMII mode are a subset of the MII signals. Therefore, Table 15-1 lists the MII signals that are used in RMII mode and the RMII function to which they correspond.
MII Signal | RMII Signal | RMII Standard Name and Function |
---|---|---|
N/A | EN0RREF_CLK | REF_CLK: Synchronous clock reference for receive, transmit and control |
EN0TXCK | Not used | N/A |
EN0TXD3 | Not used | N/A |
EN0TXD2 | Not used | N/A |
EN0TXD1 | EN0TXD1 | TXD1: Transmit Data 1 |
EN0TXD0 | EN0TXD0 | TXD0: Transmit Data 0 |
EN0TXEN | EN0TXEN | TEX_EN: Transmit Enable |
EN0TXER | Not used | N/A |
EN0RXCK | Not used | N/A |
EN0RXD3 | Not used | N/A |
EN0RXD2 | Not used | N/A |
EN0RXD1 | EN0RXD1 | RXD1: Receive Data 1 |
EN0RXD0 | EN0RXD0 | RXD0: Receive Data 0 |
EN0RXDV | EN0RXDV | CRS_DV: Carrier Sense/Receive Data Valid |
EN0RXER | Not used | RX_ER: Receive Error |
EN0COL | Not used | N/A |
EN0CRS | Not used | N/A |
EN0MDC | EN0MDC | MDC: Management Data Clock |
EN0MDIO | EN0MDIO | MDIO: Management Data Input/Output |
EN0PPS | EN0PPS | Pulse-Per-Second (PPS) Output (optional, this is not a standard RMII signal) |
EN0INTRN | EN0INTRN | Interrupt to Ethernet PHY (optional, this is not a standard RMII signal) |